Sampled-data analog signal processing is widely used in analog/digital integrated systems. With an analog-to-digital converter (ADC) and proper sampling, most signal processing functions can be achieved digitally with high accuracy, which can meet or even exceed analog signal processing accuracy. Example signal processing functions used in a variety of applications from communications to measurement include filtering, timing recovery, and demodulation.
During analog to digital conversion, the analog signal is sampled. This is typically achieved with sample-and-hold (S/H) or track-and-hold (T/H) circuits at the input that accepts the analog signal. S/H and T/H circuits hold a discrete value of the input taken at an instant of time to permit an analog to digital conversion circuit to see a fixed voltage that may be converted into a digital value. In CMOS technology, S/H is the more commonly used technique because most ADCs are implemented in switched-capacitor circuits.
T/H has advantages, however. For example, in generic high-speed flash-type architectures, T/H helps to shorten the data conversion time. FIG. 1A shows a conventional differential CMOS T/H circuit, which includes two capacitors, C1 and C2, two transistor switches, Ms1 and Ms2, and two buffer amplifiers, A1 and A2, for positive and negative inputs. Two inverters, I1 (including transistors M1-M2) and I2 (including transistors M3-M4) act as drivers to drive switches Ms1 and Ms2. When Ms1 and Ms2 are turned on, Out±tracks In±. When Ms1 and Ms2 are turned off, Out±holds the differential voltage present just before the switches Ms1 and Ms2 are turned off. If switches Ms1 and Ms2 and inverters I1 and I2 are ideal and the hold clock rises infinitely fast, the signal will be held on the two sampling capacitors C1 and C2 when the clock rises, and no error occurs in sampling. All S/H and/or T/H circuits are limited in performance by standard non-ideal factors such as jitter, kT/C noise, sampling group delay and bandwidth, and capacitor non-linearity, etc.
Due to the finite rise/fall time of the hold clock applied to the inverters I1 and I2 in FIG. 1A, the two switches Ms1 and Ms2 are turned off at different times, as illustrated graphically in FIG. 1B. For example, Out+ is sampled a little earlier than Out− in time. This signal dependent sampling time error contributes both to noise and to non-linearity. In a small signal case when both switches are turned off at about the same time, early and late sampling time errors tend to be somewhat cancelled due to the symmetry in the differential sampling. However, the asymmetry in early and late sampling times still exists for large signal sampling. Therefore, in general, this error increases with larger and higher frequency signals.
With regard to the conventional circuit of FIG. 1A, there are two principle error sources. One is the signal-dependent sampling time error and the other is the switch-related non-linearity error. In the standard bottom-plate S/H circuits, the signal-dependent sampling time error and clock feed-through error are not significant, and only the bottom-plate switch non-linearity matters.
Switch non-linearity has been addressed in S/H circuits. One technique decreases the switch on-resistance by a constant-voltage boosting of the gate over-drive voltage of the bottom-plate switch transistor. See, e.g., Cho, T. B. and Gray, P. R., “A 10-bit, 20-MS/s, 35-mW Pipeline A/D Converter,” IEEE J. of Solid-State Circuits, Vol. 30, pp. 166-172, March 1995. This technique results in a smaller voltage drop across the non-linear switch in sampling and thereby the sampling non-linearity is reduced. However, the constant-voltage boosting of the gate over-drive voltage is significantly affected by the signal-dependent switch on-resistance.
Another way is to boost the gate over-drive voltage by a constant voltage over the input signal. See, e.g., Brooks, T. L., Robertson, D. H., Kelly, D. F., Del Muro, A., and Harston, S. W., “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR,” IEEE J. of Solid-State Circuits, Vol. 32, pp. 1896-1906, December 1997. This second technique keeps the switch on-resistance relatively constant. However, the signal-dependent non-linear threshold voltage still modulates the switch on-resistance.
In S/H, the non-linearity in the switch on-resistance is a principal error source in sampling. In S/H, the non-linear threshold voltage variation of the sampling switch can be cancelled by boosting with a feedback amplifier. See, e.g., Pan, H., Segami, M., Choi, M., Ling Cao, and Abidi, A. A., “A 3.3-V 12-b 50-MS/s A/D Converter in 0.6-μm CMOS with Over 80-dB SFDR,” IEEE J. of Solid-State Circuits, Vol. 35, pp. 1769-1780, December 2000. However, in T/H, the signal-dependent non-linear channel charge injection also needs to be considered.